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june 2013 altera corporation cv-51002-3.4 datasheet ? 2013 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 101 innovation drive san jose, ca 95134 www.altera.com feedback subscribe iso 9001:2008 registered cyclone v device datasheet this datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and i/o timing for cyclone ? v devices. cyclone v devices are offered in commercial and industrial grades. commercial devices are offered in ?c6 (fastest), ?c7, and ?c8 speed grades. industrial devices are offered in the ?i7 speed grade. automotive devices are offered in the ?a7 speed grade. f for more information about the densities and packages of devices in the cyclone v family, refer to the cyclone v device overview . electrical characteristics the following sections describe the electrical characteristics of cyclone v devices. operating conditions cyclone v devices are rated according to a set of defined parameters. to maintain the highest possible performance and reliability of the cyclone v devices, you must consider the operating requirements described in this datasheet. june 2013 cv-51002-3.4
page 2 electrical characteristics cyclone v device datasheet june 2013 altera corporation absolute maximum ratings absolute maximum ratings define the maximum operating conditions for cyclone v devices. the values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. the functional operation of the device is not implied for these conditions. c conditions other than those listed in table 1 may cause permanent damage to the device. additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. table 1 lists the cyclone v absolute maximum ratings. table 1. absolute maximum ratings for cyclone v devices? preliminary symbol description minimum maximum unit v cc core voltage and periphery circuitry power supply ?0.5 1.35 v v ccpgm configuration pins power supply ?0.5 3.75 v v cc_aux auxiliary supply ?0.5 3.75 v v ccbat battery back-up power supply for design security volatile key register ?0.5 3.75 v v ccpd i/o pre-driver power supply ?0.5 3.75 v v ccio i/o power supply ?0.5 3.9 v v cca_fpll pll analog power supply ?0.5 3.75 v v cch_gxb transceiver high voltage power ?0.5 3.75 v v cce_gxb transceiver power ?0.5 1.35 v v ccl_gxb transceiver clock network power ?0.5 1.35 v v i dc input voltage ?0.5 3.80 v v cc_hps hps core voltage and periphery circuitry power supply ?0.5 1.35 v v ccpd_hps hps i/o pre-driver power supply ?0.5 3.75 v v ccio_hps hps i/o power supply ?0.5 3.9 v v ccrstclk_hps hps reset and clock input pins power supply ?0.5 3.75 v v ccpll_hps hps pll analog power supply ?0.5 3.75 v i out dc output current per pin ?25 40 ma t j operating junction temperature ?55 125 c t stg storage temperature (no bias) ?65 150 c
electrical characteristics page 3 june 2013 altera corporation cyclone v device datasheet maximum allowed overshoot and undershoot voltage during transitions, input signals may overshoot to the voltage listed in table 2 and undershoot to -2.0 v for input currents less than 100 ma and periods shorter than 20 ns. the maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. a dc signal is equivalent to 100% duty cycle. for example, a signal that overshoots to 4.00 v can only be at 4.00 v for ~15% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 1.5 years. table 2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. table 2. maximum allowed overshoot during transitions for cyclone v devices? preliminary symbol description condition (v) overshoot duration as % of high time unit vi (ac) ac input voltage 3.8 100 % 3.85 68 % 3.9 45 % 3.95 28 % 415% 4.05 13 % 4.1 11 % 4.15 9 % 4.2 8 % 4.25 7 % 4.3 5.4 % 4.35 3.2 % 4.4 1.9 % 4.45 1.1 % 4.5 0.6 % 4.55 0.4 % 4.6 0.2 %
page 4 electrical characteristics cyclone v device datasheet june 2013 altera corporation recommended operating conditions recommended operating conditions are the functional operation limits for the ac and dc parameters for cyclone v devices. table 3 lists the steady-state voltage values expected from cyclone v devices. power supply ramps must all be strictly monotonic, without plateaus. table 3. recommended operating conditions for cyclone v devices? preliminary (part 1 of 2) symbol description condition minimum typical maximum unit v cc core voltage, periphery circuitry power supply, transceiver physical coding sublayer (pcs) power supply, and transceiver pci express ? (pcie ? ) hard ip digital power supply ? 1.07 1.1 1.13 v v cc_aux auxiliary supply ? 2.375 2.5 2.625 v v ccpd (1) i/o pre-driver (3.3 v) power supply ? 3.135 3.3 3.465 v i/o pre-driver (3.0 v) power supply ? 2.85 3.0 3.15 v i/o pre-driver (2.5 v) power supply ? 2.375 2.5 2.625 v v ccio i/o buffers (3.3 v) power supply ? 3.135 3.3 3.465 v i/o buffers (3.0 v) power supply ? 2.85 3.0 3.15 v i/o buffers (2.5 v) power supply ? 2.375 2.5 2.625 v i/o buffers (1.8 v) power supply ? 1.71 1.8 1.89 v i/o buffers (1.5 v) power supply ? 1.425 1.5 1.575 v i/o buffers (1.35 v) power supply ? 1.283 1.35 1.418 v i/o buffers (1.25 v) power supply ? 1.19 1.25 1.31 v i/o buffers (1.2 v) power supply ? 1.14 1.2 1.26 v v ccpgm configuration pins (3.3 v) power supply ? 3.135 3.3 3.465 v configuration pins (3.0 v) power supply ? 2.85 3.0 3.15 v configuration pins (2.5 v) power supply ? 2.375 2.5 2.625 v configuration pins (1.8 v) power supply ? 1.71 1.8 1.89 v v cca_fpll (2) pll analog voltage regulator power supply ? 2.375 2.5 2.625 v v ccbat (3) battery back-up power supply (for design security volatile key register) ? 1.2 ? 3.0 v v i dc input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v t j operating junction temperature commercial 0 ? 85 c industrial ?40 ? 100 c automotive ?40 ? 125 c
electrical characteristics page 5 june 2013 altera corporation cyclone v device datasheet table 4 lists the transceiver power supply recommended operating conditions for cyclone v gx and gt devices. table 5 lists the steady-state voltage values expected from cyclone v system-on-a-chip (soc) fpga with arm ? -based hard processor system (hps). power supply ramps must all be strictly monotonic, without plateaus. t ramp (4) power supply ramp time standard por 200 s ? 100 ms ? fast por 200 s ? 4 ms ? notes to table 3 : (1) v ccpd must be 2.5 v when v ccio is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 v. v ccpd must be 3.0 v when v ccio is 3.0 v. v ccpd must be 3.3 v when v ccio is 3.3 v. (2) pll digital voltage is regulated from v cca_fpll . (3) if you do not use the design security feature in cyclone v devices, connect v ccbat to a 1.5-v, 2.5-v, or 3.0-v power supply. the power-on reset (por) circuitry monitors v ccbat . cyclone v devices do not exit por if v ccbat stays low. (4) this is also applicable to hps power supply. for hps power supply, refer to t ramp specifications for standard por when hps_porsel = 0 and t ramp specifications for fast por when hps_porsel = 1. table 3. recommended operating conditions for cyclone v devices? preliminary (part 2 of 2) symbol description condition minimum typical maximum unit table 4. transceiver power supply operating conditions for cyclone v gx and gt devices? preliminary symbol description minimum typical maximum unit v cch_gxbl transceiver high voltage power (left side) 2.375 2.5 2.625 v v cce_gxbl (1) , (2) transmitter and receiver power (left side) 1.07/1.17 1.1/1.2 1.13/1.23 v v ccl_gxbl (1) , (2) clock network power (left side) 1.07/1.17 1.1/1.2 1.13/1.23 v notes to table 4 : (1) altera recommends increasing the v cce_gxbl and v ccl_gxbl typical value from 1.1 v to 1.2 v for cyclone v gt fpga systems which require full compliance to the pcie gen2 transmit jitter specification. for more information about the maximum full duplex channels recommended in cyclone v gt and st devices under this condition, refer to the transceiver protocol configurations in cyclone v devices chapter. (2) altera recommends increasing the v cce_gxbl and v ccl_gxbl typical value from 1.1 v to 1.2 v for full compliance to cpri transmit jitter specification at 4.9152 gbps (cyclone v gt and st devices) and 6.144gbps (cyclone v gt devices only). for more information about the maximum full duplex channels recommended in cyclone v gt devices for cpri 6.144 gbps, refer to the transceiver protocol configurations in cyclone v devices chapter. table 5. hps power supply operating conditions for cyclone v se, sx, and st devices (1) ? preliminary (part 1 of 2) symbol description minimum typical maximum unit v cc_hps hps core voltage and periphery circuitry power supply 1.07 1.1 1.13 v v ccpd_hps (2) hps i/o pre-driver (3.3 v) power supply 3.135 3.3 3.465 v hps i/o pre-driver (3.0 v) power supply 2.85 3.0 3.15 v hps i/o pre-driver (2.5 v) power supply 2.375 2.5 2.625 v v ccio_hps hps i/o buffers (3.3 v) power supply 3.135 3.3 3.465 v hps i/o buffers (3.0 v) power supply 2.85 3.0 3.15 v hps i/o buffers (2.5 v) power supply 2.375 2.5 2.625 v hps i/o buffers (1.8 v) power supply 1.71 1.8 1.89 v hps i/o buffers (1.5 v) power supply 1.425 1.5 1.575 v hps i/o buffers (1.2 v) power supply 1.14 1.2 1.26 v
page 6 electrical characteristics cyclone v device datasheet june 2013 altera corporation dc characteristics this section lists the following specifications: supply current and power consumption i/o pin leakage current bus hold specifications oct specifications pin capacitance hot socketing supply current and power consumption standby current is the current drawn from the respective power rails used for power budgeting. altera offers two ways to estimate power for your design?the excel-based early power estimator (epe) and the quartus ? ii powerplay power analyzer feature. use the excel-based early power estimator (epe) before you start your design to estimate the supply current for your design. the epe provides a magnitude estimate of the device power because these currents vary greatly with the resources you use. the quartus ii powerplay power analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. the powerplay power analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook . v ccrstclk_hps hps reset and clock input pins (3.3 v) power supply 3.135 3.3 3.465 v hps reset and clock input pins (3.0 v) power supply 2.85 3.0 3.15 v hps reset and clock input pins (2.5 v) power supply 2.375 2.5 2.625 v hps reset and clock input pins (1.8 v) power supply 1.71 1.8 1.89 v v ccpll_hps hps pll analog voltage regulator power supply 2.375 2.5 2.625 v v cc_aux_shared hps and fpga shared auxiliary power supply 2.375 2.5 2.625 v notes to table 5 : (1) refer to table 3 for the steady-state voltage values expected from the fpga portion of the cyclone v system-on-a-chip (soc) fpgas. (2) v ccpd_hps must be 2.5 v when v ccio_hps is 2.5, 1.8, 1.5, or 1.2 v. v ccpd_hps must be 3.0 v when v ccio_hps is 3.0 v. v ccpd_hps must be 3.3 v when v ccio_hps is 3.3 v. table 5. hps power supply operating conditions for cyclone v se, sx, and st devices (1) ? preliminary (part 2 of 2) symbol description minimum typical maximum unit
electrical characteristics page 7 june 2013 altera corporation cyclone v device datasheet i/o pin leakage current table 6 lists the cyclone v i/o pin leakage current specifications. bus hold specifications table 7 lists the cyclone v device bus hold specifications. the bus-hold trip points are based on calculated input voltages from the jedec standard. table 6. i/o pin leakage current for cyclone v devices? preliminary symbol description conditions min typ max unit i i input pin v i =0vtov cciomax ?30 ? 30 a i oz tri-stated i/o pin v o =0vtov cciomax ?30 ? 30 a table 7. bus hold parameters for cyclone v devices? preliminary parameter symbol conditions v ccio (v) unit 1.2 1.5 1.8 2.5 3.0 3.3 min max min max min max min max min max min max bus-hold, low, sustaining current i susl v in >v il (max.) 8 ? 12 ? 30?50?70?70?a bus-hold, high, sustaining current i sush v in page 8 electrical characteristics cyclone v device datasheet june 2013 altera corporation oct specifications if you enable on-chip termination (oct) calibration, calibration is automatically performed at power up for i/os connected to the calibration block. table 8 lists the cyclone v oct termination calibration accuracy specifications. the oct calibration accuracy is valid at the time of calibration only. 1 calibration accuracy for the calibrated on-chip series termination (r s oct) and on-chip parallel termination (r t oct) are applicable at the moment of calibration. when process, voltage, and temperature (pvt) conditions change after calibration, the tolerance may change. table 8. oct calibration accuracy specifications for cyclone v devices symbol description conditions (v) calibration accuracy unit ?c6 ?c7, ?i7 ?c8, ?a7 25- r s internal series termination with calibration (25- setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 15 15 15 % 50- r s internal series termination with calibration (50- setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 15 15 15 % 34- and 40- r s internal series termination with calibration (34- and 40- setting) v ccio = 1.5, 1.35, 1.25, 1.2 15 15 15 % 48- , 60 - , and 80- r s internal series termination with calibration (48- , 60- , and 80- setting) v ccio = 1.2 15 15 15 % 50- r t internal parallel termination with calibration (50- setting) v ccio = 2.5, 1.8, 1.5, 1.2 -10 to +40 -10 to +40 -10 to +40 % 20- , 30- , 40- , 60- , and 120- r t internal parallel termination with calibration (20- , 30- , 40- , 60- , and 120- setting) v ccio = 1.5, 1.35, 1.25 -10 to +40 -10 to +40 -10 to +40 % 60- and 120- r t internal parallel termination with calibration (60- and 120- setting) v ccio = 1.2 -10 to +40 -10 to +40 -10 to +40 % 25- r s_left_shift internal left shift series termination with calibration (25- r s_left_shift setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 15 15 15 %
electrical characteristics page 9 june 2013 altera corporation cyclone v device datasheet table 9 lists the cyclone v oct without calibration resistance tolerance to pvt changes. use table 10 to determine the oct variation after power-up calibration and equation 1 to determine the oct variation without recalibration. table 9. oct without calibration resistance tolerance specifications for cyclone v devices? preliminary symbol description conditions (v) resistance tolerance unit ?c6 ?c7, ?i7 ?c8, ?a7 25- r s internal series termination without calibration (25- setting) v ccio = 3.0 and 2.5 30 40 40 % 25- r s internal series termination without calibration (25- setting) v ccio = 1.8 and 1.5 30 40 40 % 25- r s internal series termination without calibration (25- setting) v ccio = 1.2 35 50 50 % 50- r s internal series termination without calibration (50- setting) v ccio = 3.0 and 2.5 30 40 40 % 50- r s internal series termination without calibration (50- setting) v ccio = 1.8 and 1.5 30 40 40 % 50- r s internal series termination without calibration (50- setting) v ccio = 1.2 35 50 50 % 100- r d internal differential termination (100- setting) v ccio = 2.5 25 40 40 % equation 1. oct variation without recalibration (1) , (2) , (3) , (4) , (5) , (6) ? preliminary notes to equation 1 : (1) the r oct value calculated from equation 1 shows the range of oct resistance with the variation of temperature and v ccio . (2) r scal is the oct resistance value at power-up. (3) t is the variation of temperature with respect to the temperature at power up. (4) v is the variation of voltage with respect to v ccio at power up. (5) dr/dt is the percentage change of r scal with temperature. (6) dr/dv is the percentage change of r scal with voltage. r oct r scal 1 dr dt ------ - t ?? dr dv ------- v ?? + ?? ?? =
page 10 electrical characteristics cyclone v device datasheet june 2013 altera corporation table 10 lists the oct variation with temperature and voltage after the power-up calibration. the oct variation is valid for a v ccio range of 5% and a temperature range of 0 to 85c. pin capacitance table 11 lists the cyclone v device family pin capacitance. hot socketing table 12 lists the hot socketing specifications for cyclone v devices. table 10. oct variation after power-up calibration for cyclone v devices symbol description v ccio (v) typical unit dr/dv oct variation with voltage without recalibration 3.0 0.100 %/mv 2.5 0.100 1.8 0.100 1.5 0.100 1.35 0.150 1.25 0.150 1.2 0.150 dr/dt oct variation with temperature without recalibration 3.0 0.189 %/c 2.5 0.208 1.8 0.266 1.5 0.273 1.35 0.200 1.25 0.200 1.2 0.317 table 11. pin capacitance for cyclone v devices symbol description value unit c iotb input capacitance on top and bottom i/o pins 5.5 pf c iolr input capacitance on left and right i/o pins 5.5 pf c outfb input capacitance on dual-purpose clock output and feedback pins 5.5 pf table 12. hot socketing specifications for cyclone v devices? preliminary symbol description maximum i iopin (dc) dc current per i/o pin 300 a i iopin (ac) ac current per i/o pin 8 ma (1) i xcvr-tx (dc) dc current per transceiver transmitter (tx) pin 100 ma i xcvr-rx (dc) dc current per transceiver receiver (rx) pin 50 ma note to table 12 : (1) the i/o ramp rate is 10 ns or more. for ramp rates faster than 10 ns, |i iopin | = c dv/dt, in which c is the i/o pin capacitance and dv/dt is the slew rate.
electrical characteristics page 11 june 2013 altera corporation cyclone v device datasheet internal weak pull-up resistor table 13 lists the weak pull-up resistor values for cyclone v devices. all i/o pins have an option to enable weak pull-up except the configuration, test, and jtag pins. for more information about the pins that support internal weak pull-up and internal weak pull-down features, refer to the cyclone v device family pin connection guidelines . i/o standard specifications table 14 through table 19 list the input voltage (v ih and v il ), output voltage (v oh and v ol ), and current drive characteristics (i oh and i ol ) for various i/o standards supported by cyclone v devices. for an explanation of terms used in table 14 through table 19 , refer to ?glossary? on page 1?54 . table 13. internal weak pull-up resistor values for cyclone v devices? preliminary symbol description conditions (v) (1) typ (2) unit r pu value of the i/o pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. v ccio = 3.3 5% 25 k v ccio = 3.0 5% 25 k v ccio = 2.5 5% 25 k v ccio = 1.8 5% 25 k v ccio = 1.5 5% 25 k v ccio = 1.35 5% 25 k v ccio = 1.25 5% 25 k v ccio = 1.2 5% 25 k notes to table 13 : (1) pin pull-up resistance values may be lower if an external source drives the pin higher than v ccio . (2) these specifications are valid with 10% tolerances to cover changes over pvt. table 14. single-ended i/o standards for cyclone v devices? preliminary (part 1 of 2) i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (1) (ma) i oh (1) (ma) min typ max min max min max max min 3.3-v lvttl 3.135 3.3 3.465 ?0.3 0.8 1.7 3.6 0.45 2.4 4 ?4 3.3-v lvcmos 3.135 3.3 3.465 ?0.3 0.8 1.7 3.6 0.2 v ccio ? 0.2 2 ?2 3.0-v lvttl 2.85 3 3.15 ?0.3 0.8 1.7 3.6 0.4 2.4 2 ?2 3.0-v lvcmos 2.85 3 3.15 ?0.3 0.8 1.7 3.6 0.2 v ccio ? 0.2 0.1 ?0.1 3.0-v pci 2.85 3 3.15 ? 0.3 x v ccio 0.5 x v ccio v ccio + 0.3 0.1 x v ccio 0.9 x v ccio 1.5 ?0.5 3.0-v pci-x 2.85 3 3.15 ? 0.35 x v ccio 0.5 x v ccio v ccio + 0.3 0.1 x v ccio 0.9 x v ccio 1.5 ?0.5 2.5 v 2.375 2.5 2.625 ?0.3 0.7 1.7 3.6 0.4 2 1 ?1 1.8 v 1.71 1.8 1.89 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.45 v ccio ? 0.45 2 ?2 1.5 v 1.425 1.5 1.575 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.25 x v ccio 0.75 x v ccio 2?2
page 12 electrical characteristics cyclone v device datasheet june 2013 altera corporation 1.2 v 1.14 1.2 1.26 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.25 x v ccio 0.75 x v ccio 2?2 note to table 14 : (1) to meet the i ol and i oh specifications, you must set the current strength settings accordingly. for example, to meet the 3.3-v lvttl specification (4 ma), you should set the current strength settings to 4 ma. setting at lower current strength may not meet the i ol and i oh specifications in the handbook. table 14. single-ended i/o standards for cyclone v devices? preliminary (part 2 of 2) i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (1) (ma) i oh (1) (ma) min typ max min max min max max min table 15. single-ended sstl, hstl, and hsul i/o reference voltage specifications for cyclone v devices? preliminary i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio v ref ? 0.04 v ref v ref + 0.04 sstl-18 class i, ii 1.71 1.8 1.89 0.833 0.9 0.969 v ref ? 0.04 v ref v ref + 0.04 sstl-15 class i, ii 1.425 1.5 1.575 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio sstl-135 class i, ii 1.283 1.35 1.418 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio sstl-125 class i, ii 1.19 1.25 1.26 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio hstl-18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 ? v ccio /2 ? hstl-15 class i, ii 1.425 1.5 1.575 0.68 0.75 0.9 ? v ccio /2 ? hstl-12 class i, ii 1.14 1.2 1.26 0.47 x v ccio 0.5 x v ccio 0.53 x v ccio ?v ccio /2 ? hsul-12 1.14 1.2 1.3 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio ??? table 16. single-ended sstl, hstl, and hsul i/o standards signal specifications for cyclone v devices? preliminary (part 1 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (1) (ma) i oh (1) (ma) min max min max max min max min sstl-2 class i ?0.3 v ref ? 0.15 v ref + 0.15 v ccio + 0.3 v ref ? 0.31 v ref + 0.31 v tt ? 0.608 v tt + 0.608 8.1 ?8.1 sstl-2 class ii ?0.3 v ref ? 0.15 v ref + 0.15 v ccio + 0.3 v ref ? 0.31 v ref + 0.31 v tt ? 0.81 v tt + 0.81 16.2 ?16.2 sstl-18 class i ?0.3 v ref ? 0.125 v ref + 0.125 v ccio + 0.3 v ref ? 0.25 v ref + 0.25 v tt ? 0.603 v tt + 0.603 6.7 ?6.7 sstl-18 class ii ?0.3 v ref ? 0.125 v ref + 0.125 v ccio + 0.3 v ref ? 0.25 v ref + 0.25 0.28 v ccio ? 0.28 13.4 ?13.4 sstl-15 class i ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.175 v ref + 0.175 0.2 x v ccio 0.8 x v ccio 8?8
electrical characteristics page 13 june 2013 altera corporation cyclone v device datasheet sstl-15 class ii ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.175 v ref + 0.175 0.2 x v ccio 0.8 x v ccio 16 ?16 sstl-135 ?v ref ? 0.09 v ref + 0.09 ? v ref ? 0.16 v ref + 0.16 0.2 x v ccio 0.8 x v ccio ?? sstl-125 ?v ref ? 0.85 v ref + 0.85 ? v ref ? 0.15 v ref + 0.15 0.2 x v ccio 0.8 x v ccio ?? hstl-18 class i ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 8 ?8 hstl-18 class ii ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 16 ?16 hstl-15 class i ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 8 ?8 hstl-15 class ii ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 16 ?16 hstl-12 class i ?0.1 5 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 v ref ? 0.15 v ref + 0.15 0.25 x v ccio 0.75 x v ccio 8?8 hstl-12 class ii ?0.1 5 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 v ref ? 0.15 v ref + 0.15 0.25 x v ccio 0.75 x v ccio 16 ?16 hsul-12 ?v ref ? 0.13 v ref + 0.13 ? v ref ? 0.22 v ref + 0.22 0.1 x v ccio 0.9 x v ccio ?? note to table 16 : (1) to meet the i ol and i oh specifications, you must set the current strength settings accordingly. for example, to meet the sstl15ci specification (8 ma), you should set the current strength settings to 8 ma. setting at lower current strength may not meet the i ol and i oh specifications in the handbook. table 16. single-ended sstl, hstl, and hsul i/o standards signal specifications for cyclone v devices? preliminary (part 2 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (1) (ma) i oh (1) (ma) min max min max max min max min table 17. differential sstl i/o standards for cyclone v devices? preliminary i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) min typ max min max min typ max min max sstl-2 class i, ii 2.375 2.5 2.625 0.3 v ccio + 0.6 v ccio /2 ? 0.2 ? v ccio /2 + 0.2 0.62 v ccio + 0.6 sstl-18 class i, ii 1.71 1.8 1.89 0.25 v ccio + 0.6 v ccio /2 ? 0.175 ? v ccio /2 + 0.175 0.5 v ccio + 0.6 sstl-15 class i, ii 1.425 1.5 1.575 0.2 (1) v ccio /2 ? 0.15 ? v ccio /2 + 0.15 2(v ih(ac) ? v ref ) 2(v il(ac) ? v ref ) sstl-135 1.283 1.35 1.45 0.18 (1) v ccio /2 ? 0.15 v ccio /2 v ccio /2 + 0.15 2(v ih(ac) ? v ref ) 2(v il(ac) ? v ref ) sstl-125 1.19 1.25 1.31 0.18 (1) v ccio /2 ? 0.15 v ccio /2 v ccio /2 + 0.15 2(v ih(ac) ? v ref ) 2(v il(ac) ? v ref ) note to table 17 : (1) the maximum value for v swing(dc) is not defined. however, each single-ended signal needs to be within the respective single-ended limits (v ih(dc) and v il(dc) ).
page 14 electrical characteristics cyclone v device datasheet june 2013 altera corporation table 18. differential hstl and hsul i/o standards for cyclone v devices? preliminary i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max min max hstl-18 class i, ii 1.71 1.8 1.89 0.2 ? 0.78 ? 1.12 0.78 ? 1.12 0.4 ? hstl-15 class i, ii 1.425 1.5 1.575 0.2 ? 0.68 ? 0.9 0.68 ? 0.9 0.4 ? hstl-12 class i, ii 1.14 1.2 1.26 0.16 v ccio + 0.3 ? 0.5 x v ccio ? 0.4 x v ccio 0.5 x v ccio 0.6 x v ccio 0.3 v ccio + 0.48 hsul-12 1.14 1.2 1.3 0.26 0.26 0.5 x v ccio ? 0.12 0.5 x v ccio 0.5 x v ccio +0.12 0.4 x v ccio 0.5 x v ccio 0.6 x v ccio 0.44 0.44 table 19. differential i/o standard specifications for cyclone v devices? preliminary i/o standard v ccio (v) v id (mv) (1) v icm(dc) (v) v od (v) (2) v ocm (v) (2) min typ max min condition max min condition max min typ max min typ max pcml transmitter, receiver, and input reference clock pins of high-speed transceivers use the pcml i/o standard. for transmitter, receiver, and reference clock i/o pin specifications, refer to table 20 . 2.5 v lvds (3) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 d max 700 mbps 1.80 0.247 ? 0.6 1.125 1.25 1.375 1.05 d max >700 mbps 1.55 rsds (hio) (4) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.25 ? 1.45 0.1 0.2 0.6 0.5 1.2 1.4 mini-lvds (hio) (5) 2.375 2.5 2.625 200 ? 600 0.300 ? 1.425 0.25 ? 0.6 1 1.2 1.4 lvpecl (6) 2.375 2.5 2.625 300 ? ? 0.60 d max 700 mbps 1.80 ??? ? ? ? 1.00 d max >700 mbps 1.60 slvs 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 ? 1.8 ? ? ? ? ? ? sub-lvds 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 ? 1.8 ? ? ? ? ? ? hispi 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 ? 1.8 ? ? ? ? ? ? notes to table 19 : (1) the minimum v id value is applicable over the entire common mode range, v cm . (2) r l range: 90 r l 110 (3) for optimized lvds receiver performance, the receiver voltage input range must be within 1.0 v to 1.6 v for data rate above 700 mbps and 0.00 v to 1.85 v for data rate below 700 mbps. (4) for optimized rsds receiver performance, the receiver voltage input range must be within 0.25 v to 1.45 v. (5) for optimized mini-lvds receiver performance, the receiver voltage input range must be within 0.300 v to 1.425 v. (6) for optimized lvpecl receiver performance, the receiver voltage input range must be within 0.85 v to 1.75 v for data rate above 700 mbps and 0.45 v to 1.95 v for data rate below 700 mbps.
switching characteristics page 15 june 2013 altera corporation cyclone v device datasheet switching characteristics this section provides performance characteristics of cyclone v core and periphery blocks for commercial grade devices. transceiver performance specifications this section describes transceiver performance specifications. table 20 lists the cyclone v gx, gt, sx, and st transceiver specifications. table 20. transceiver specifications for cyclone v gx, gt, sx, and st devices? preliminary (part 1 of 4) symbol/ description conditions transceiver speed grade 5 (1) transceiver speed grade 6 transceiver speed grade 7 unit min typ max min typ max min typ max reference clock supported i/o standards 1.2 v pcml, 1.5 v pcml, 2.5 v pcml, differential lvpecl (2) , hcsl , and lvds input frequency from refclk input pins (3) ? 27 ? 550 27 ? 550 27 ? 550 mhz rise time 20% to 80% of rising clock edge ? ? 250 ? ? 250 ? ? 250 ps fall time 80% to 20% of falling clock edge ? ? 250 ? ? 250 ? ? 250 ps duty cycle ? 45 ? 55 45 ? 55 45 ? 55 % peak-to-peak differential input voltage ? 200 ? 2000 200 ? 2000 200 ? 2000 mv spread-spectrum modulating clock frequency pcie 30 ? 33 30 ? 33 30 ? 33 khz spread-spectrum downspread pcie ? 0to ?0.5% ?? 0to ?0.5% ?? 0to ?0.5% ?? on-chip termination resistors ? ? 100 ? ? 100 ? ? 100 ? v icm (ac coupled) ? v cce_gxbl supply (5) , (6) v cce_gxbl supply v cce_gxbl supply v v icm (dc coupled) hcsl i/o standard for the pcie reference clock 250 ? 550 250 ? 550 250 ? 550 mv transmitter refclk phase noise (4) 10 hz ? ? ?50 ? ? ?50 ? ? ?50 dbc/hz 100 hz ? ? ?80 ? ? ?80 ? ? ?80 dbc/hz 1 khz ? ? ?110 ? ? ?110 ? ? ?110 dbc/hz 10 khz ? ? ?120 ? ? ?120 ? ? ?120 dbc/hz 100 khz ? ? ?120 ? ? ?120 ? ? ?120 dbc/hz 1 mhz ? ? ?130 ? ? ?130 ? ? ?130 dbc/hz
page 16 switching characteristics cyclone v device datasheet june 2013 altera corporation r ref ?? 2000 1% ?? 2000 1% ?? 2000 1% ? transceiver clocks fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? ? 125 ? mhz transceiver reconfiguration controller ip ( mgmt_clk_clk ) clock frequency ?75? 100/ 125 (7) 75 ? 100/ 125 (7) 75 ? 100/ 125 (7) mhz receiver supported i/o standards 1.5 v pcml , 2.5 v pcml , lvpecl , and lvds data rate ? 614 ? 5000/ 6144 (8) 614 ? 3125 614 ? 2500 mbps absolute v max for a receiver pin (9) ? ? ? 1.2 ? ? 1.2 ? ? 1.2 v absolute v min for a receiver pin ? ?0.4 ? ? ?0.4 ? ? ?0.4 ? ? v maximum peak-to-peak differential input voltage v id (diff p-p) before device configuration ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v maximum peak-to-peak differential input voltage v id (diff p-p) after device configuration ? ? ? 2.2 ? ? 2.2 ? ? 2.2 v minimum differential eye opening at the receiver serial input pins (10) ?85??85??85??mv differential on-chip termination resistors 85 ? setting ? 85 ? ? 85 ? ? 85 ? 100 ? setting ? 100 ? ? 100 ? ? 100 ? 120 ? setting ? 120 ? ? 120 ? ? 120 ? 150- setting ? 150 ? ? 150 ? ? 150 ? v icm (ac coupled) 2.5 v pcml , lvpecl , and lvds v cce_gxbl supply (5) , (6) v cce_gxbl supply v cce_gxbl supply v 1.5 v pcml 0.7 v t ltr (11) ???10??10??10s t ltd (12) ???4??4??4s t ltd_manual (13) ???4??4??4s table 20. transceiver specifications for cyclone v gx, gt, sx, and st devices? preliminary (part 2 of 4) symbol/ description conditions transceiver speed grade 5 (1) transceiver speed grade 6 transceiver speed grade 7 unit min typ max min typ max min typ max
switching characteristics page 17 june 2013 altera corporation cyclone v device datasheet t ltr_ltd_manual (14) ?15??15??15??s programmable ppm detector (15) ? 62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm run length ? ? ? 200 ? ? 200 ? ? 200 ui programmable equalization (ac) and dc gain ? refer to figure 1 and figure 2 db transmitter supported i/o standards 1.5 v pcml data rate ? 614 ? 5000/ 6144 (8) 614 ? 3125 614 ? 2500 mbps v ocm (ac coupled) ? ? 650 ? ? 650 ? ? 650 ? mv differential on-chip termination resistors 85 ? setting ? 85 ? ? 85 ? ? 85 ? 100 ? setting ? 100 ? ? 100 ? ? 100 ? 120 ? setting ? 120 ? ? 120 ? ? 120 ? 150- setting ? 150 ? ? 150 ? ? 150 ? rise time (16) ? 30 ? 160 30 ? 160 30 ? 160 ps fall time (16) ? 30 ? 160 30 ? 160 30 ? 160 ps cmu pll supported data range ? 614 ? 5000/ 6144 (8) 614 ? 3125 614 ? 2500 mbps fpll supported data range ? 614 ? 3125 614 ? 3125 614 ? 3125 mbps transceiver-fpga fabric interface interface speed (single-width mode) ? 25 ? 187.5 25 ? 163.84 25 ? 156.25 mhz table 20. transceiver specifications for cyclone v gx, gt, sx, and st devices? preliminary (part 3 of 4) symbol/ description conditions transceiver speed grade 5 (1) transceiver speed grade 6 transceiver speed grade 7 unit min typ max min typ max min typ max
page 18 switching characteristics cyclone v device datasheet june 2013 altera corporation interface speed (double-width mode) ? 25 ? 163.84 25 ? 163.84 25 ? 156.25 mhz notes to table 20 : (1) transceiver speed grade 5 covers specifications for cyclone v gt and st devices. (2) differential lvpecl signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table. (3) the reference clock frequency must be 307.2 mhz to be fully compliance to cpri transmit jitter specification at 6.144 gbps. for more information about cpri 6.144 gbps, refer to the transceiver protocol configurations in cyclone v devices chapter. (4) the transmitter refclk phase jitter is 30 ps p-p at bit error rate (ber) 10 -12 . (5) altera recommends increasing the v cce_gxbl and v ccl_gxbl typical value from 1.1 v to 1.2 v for cyclone v gt fpga systems which require full compliance to the pcie gen2 transmit jitter specification. for more information about the maximum full duplex channels recommended in cyclone v gt and st devices under this condition, refer to the transceiver protocol configurations in cyclone v devices chapter. (6) altera recommends increasing the v cce_gxbl and v ccl_gxbl typical value from 1.1 v to 1.2 v for full compliance to cpri transmit jitter specification at 4.9152 gbps (cyclone v gt and st devices) and 6.144 gbps (cyclone v gt devices only). for more information about the maximum full duplex channels recommended in cyclone v gt devices for cpri 6.144 gbps, refer to the transceiver protocol configurations in cyclone v devices chapter. (7) the maximum supported clock frequency is 100 mhz if the pcie hard ip block is enabled or 125 mhz if the pcie hard ip block is not enabled. (8) cyclone v gt devices support up to three full duplex channels that is compliant to 6144-mbps cpri protocol in every two transceiver banks. for cpri 6144-mbps transmit jitter compliance, altera recommends that you use only up to three full-duplex transceiver channels for two transceiver banks in cpri mode. the transceivers are a grouped in transceiver banks of three channels. for more information about the transceiver bank, refer to the transceiver architecture in cyclone v devices chapter. (9) the device cannot tolerate prolonged operation at this absolute maximum. (10) the differential eye opening specification at the receiver input pins assumes that you have disabled the receiver equalization feature. if you enable the receiver equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (11) t ltr is the time required for the receive cdr to lock to the input reference clock frequency after coming out of reset. (12) t ltd is time required for the receiver cdr to start recovering valid data after the rx_is_lockedtodata signal goes high. (13) t ltd_manual is the time required for the receiver cdr to start recovering valid data after the rx_is_lockedtodata signal goes high when the cdr is functioning in the manual mode. (14) t ltr_ltd_manual is the time the receiver cdr must be kept in lock to reference (ltr) mode after the rx_is_lockedtoref signal goes high when the cdr is functioning in the manual mode. (15) the rate matcher supports only up to 300 parts per million (ppm). (16) the quartus ii software automatically selects the appropriate slew rate depending on the configured data rate or functional mode. table 20. transceiver specifications for cyclone v gx, gt, sx, and st devices? preliminary (part 4 of 4) symbol/ description conditions transceiver speed grade 5 (1) transceiver speed grade 6 transceiver speed grade 7 unit min typ max min typ max min typ max
switching characteristics page 19 june 2013 altera corporation cyclone v device datasheet figure 1 shows the continuous time-linear equalizer (ctle) response for cyclone v devices with data rates > 3.25 gbps. figure 1. ctle response for cyclone v devices with data rates > 3.25 gbps
page 20 switching characteristics cyclone v device datasheet june 2013 altera corporation figure 2 shows the ctle response for cyclone v devices with data rates 3.25 gbps. figure 2. ctle response for cyclone v devices with data rates 3.25 gbps
switching characteristics page 21 june 2013 altera corporation cyclone v device datasheet table 21 lists the tx v od settings for cyclone v transceiver channels. table 21. typical tx v od setting for cyclone v transceiver channels = 100 ? preliminary symbol v od setting (1) v od value (mv) v od setting (1) v od value (mv) v od differential peak to peak typical 0 0 32 640 1 20 33 660 2 40 34 680 3 60 35 700 4 80 36 720 5 100 37 740 6 120 38 760 7 140 39 780 8 160 40 800 9 180 41 820 10 200 42 840 11 220 43 860 12 240 44 880 13 260 45 900 14 280 46 920 15 300 47 940 16 320 48 960 17 340 49 980 18 360 50 1000 19 380 51 1020 20 400 52 1040 21 420 53 1060 22 440 54 1080 23 460 55 1100 24 480 56 1120 25 500 57 1140 26 520 58 1160 27 540 59 1180 28 560 60 1200 29 580 61 1220 30 600 62 1240 31 620 63 1260 note to table 21 : (1) convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for pma analog controls.
page 22 switching characteristics cyclone v device datasheet june 2013 altera corporation table 22 lists the simulation data on the transmitter pre-emphasis levels in db for the first post tap under the following conditions: low-frequency data pattern?five 1s and five 0s data rate?2.5 gbps the levels listed are a representation of possible pre-emphasis levels under the specified conditions only and the pre-emphasis levels may change with data pattern and data rate. 1 to predict the pre-emphasis level for your specific data rate and pattern, run simulations using the cyclone v hssi hspice models. table 22. transmitter pre-emphasis levels for cyclone v devices (1) , (2) , (3) , (4) ? preliminary (part 1 of 2) quartus ii 1st post tap pre-emphasis setting quartus ii v od setting unit 10 (200 mv) 20 (400 mv) 30 (600 mv) 35 (700 mv) 40 (800 mv) 45 (900 mv) 50 (1000 mv) 0 0000000db 1 1.97 0.88 0.43 0.32 0.24 0.19 0.13 db 2 3.58 1.67 0.95 0.76 0.61 0.5 0.41 db 3 5.35 2.48 1.49 1.2 1 0.83 0.69 db 4 7.27 3.31 2 1.63 1.36 1.14 0.96 db 5 ? 4.19 2.55 2.1 1.76 1.49 1.26 db 6 ? 5.08 3.11 2.56 2.17 1.83 1.56 db 7 ? 5.99 3.71 3.06 2.58 2.18 1.87 db 8 ? 6.92 4.22 3.47 2.93 2.48 2.11 db 9 ? 7.92 4.86 4 3.38 2.87 2.46 db 10 ? 9.04 5.46 4.51 3.79 3.23 2.77 db 11 ? 10.2 6.09 5.01 4.23 3.61 ? db 12 ? 11.56 6.74 5.51 4.68 3.97 ? db 13 ? 12.9 7.44 6.1 5.12 4.36 ? db 14 ? 14.44 8.12 6.64 5.57 4.76 ? db 15 ? ? 8.87 7.21 6.06 5.14 ? db 16 ? ? 9.56 7.73 6.49 ? ? db 17 ? ? 10.43 8.39 7.02 ? ? db 18 ? ? 11.23 9.03 7.52 ? ? db 19 ? ? 12.18 9.7 8.02 ? ? db 20 ? ? 13.17 10.34 8.59 ? ? db 21 ? ? 14.2 11.1 ? ? ? db 22 ? ? 15.38 11.87 ? ? ? db 23 ? ? ? 12.67 ? ? ? db 24 ? ? ? 13.48 ? ? ? db
switching characteristics page 23 june 2013 altera corporation cyclone v device datasheet 25 ? ? ? 14.37 ? ? ? db 26 ???????db 27 ???????db 28 ???????db 29 ???????db 30 ???????db 31 ???????db notes to table 22 : (1) the 1st post tap pre-emphasis settings must satisfy |b| + |c| 60 |b|=v od setting with termination value, r term = 100 |c| = 1st post tap pre-emphasis setting (2) |b| ? |c| > 5 for data rate s < 5 gbps and |b| ? |c| > 8.25 for data rate s > 5 gbps. (3) (v max /v min ? 1)% < 600%, where v max = |b| + |c| and v min = |b| ? |c|. (4) for example, when v od = 800 mv, the corresponding v od value setting is 40. to check the validity of the 1st post tap pre-emphasis setting = 2 |b| + |c| 60 40+2=42 |b| ?|c| > 5 40?2=38 (v max /v min ? 1)% < 600% (42/38 ? 1)% = 10.52% therefore, the 1st post tap pre-emphasis settin g=2isa valid condition. table 22. transmitter pre-emphasis levels for cyclone v devices (1) , (2) , (3) , (4) ? preliminary (part 2 of 2) quartus ii 1st post tap pre-emphasis setting quartus ii v od setting unit 10 (200 mv) 20 (400 mv) 30 (600 mv) 35 (700 mv) 40 (800 mv) 45 (900 mv) 50 (1000 mv)
page 24 switching characteristics cyclone v device datasheet june 2013 altera corporation core performance specifications this section describes the clock tree, phase-locked loop (pll), digital signal processing (dsp), and memory block specifications. clock tree specifications table 23 lists the clock tree specifications for cyclone v devices. pll specifications table 24 lists the cyclone v pll specifications when operating in the commercial (0 to 85c), industrial (?40 to 100c), and automotive (?40 to 125c) junction temperature ranges. table 23. clock tree performance for cyclone v devices? preliminary parameter performance unit ?c6 ?c7, ?i7 ?c8, ?a7 global clock and regional clock 550 550 460 mhz peripheral clock 155 155 155 mhz table 24. pll specifications for cyclone v devices (1) ? preliminary (part 1 of 3) symbol parameter min typ max unit f in input clock frequency ?c6 speed grade 5 ? 670 (2) mhz ?c7, ?i7 speed grades 5 ? 622 (2) mhz ?c8, ?a7 speed grades 5 ? 500 (2) mhz f inpfd integer input clock frequency to the pfd 5 ? 325 mhz f finpfd fractional input clock frequency to the pfd 50 ? tbd (1) mhz f vco (3) pll vco operating range ?c6 speed grade 600 ? 1600 mhz ?c7, ?i7 speed grades 600 ? 1400 mhz ?c8, ?a7 speed grades 600 ? 1300 mhz t einduty input clock or external feedback clock input duty cycle 40 ? 60 % f out output frequency for internal global or regional clock ?c6 speed grade ? ? 550 (4) mhz ?c7, ?i7 speed grades ? ? 550 (4) mhz ?c8, ?a7 speed grades ? ? 460 (4) mhz f out_ext output frequency for external clock output ?c6 speed grade ? ? 667 (4) mhz ?c7, ?i7 speed grades ? ? 667 (4) mhz ?c8, ?a7 speed grades ? ? 533 (4) mhz t outduty duty cycle for external clock output (when set to 50%) 45 50 55 % t fcomp external feedback clock compensation time ? ? 10 ns t dyconfigclk dynamic configuration clock ? ? 100 mhz t lock time required to lock from end-of-device configuration or deassertion of areset ?? 1 ms t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) ?? 1 ms
switching characteristics page 25 june 2013 altera corporation cyclone v device datasheet f clbw pll closed-loop low bandwidth ? 0.3 ? mhz pll closed-loop medium bandwidth ? 1.5 ? mhz pll closed-loop high bandwidth (9) ? 4 ? mhz t pll_pserr accuracy of pll phase shift ? ? 50 ps t areset minimum pulse width on the areset signal 10 ? ? ns t inccj (5) , (6) input clock cycle-to-cycle jitter (f ref 100 mhz) ? ? 0.15 ui (p-p) input clock cycle-to-cycle jitter (f ref < 100 mhz) ? ? 750 ps (p-p) t outpj_dc (7) period jitter for dedicated clock output (f out 100 mhz) ? ? tbd (1) ps (p-p) period jitter for dedicated clock output (f out < 100 mhz) ? ? tbd (1) mui (p-p) t outccj_dc (7) cycle-to-cycle jitter for dedicated clock output (f out 100 mhz) ? ? tbd (1) ps (p-p) cycle-to-cycle jitter for dedicated clock output (f out < 100 mhz) ? ? tbd (1) mui (p-p) t outpj_io (7) , (10) period jitter for clock output on regular i/o (f out 100 mhz) ? ? tbd (1) ps (p-p) period jitter for clock output on regular i/o (f out < 100 mhz) ? ? tbd (1) mui (p-p) t outccj_io (7) , (10) cycle-to-cycle jitter for clock output on regular i/o (f out 100 mhz) ? ? tbd (1) ps (p-p) cycle-to-cycle jitter for clock output on regular i/o (f out < 100 mhz) ? ? tbd (1) mui (p-p) t outpj_dc_f period jitter for dedicated clock output in fractional mode ? ? tbd (1) ? t outccj_dc_f cycle-to-cycle jitter for dedicated clock output in fractional mode ? ? tbd (1) ? t outpj_io_f period jitter for clock output on regular i/o in fractional mode ? ? tbd (1) ? t outccj_io_f cycle-to-cycle jitter for clock output on regular i/o in fractional mode ? ? tbd (1) ? t casc_outpj_dc (7) , (8) period jitter for dedicated clock output in cascaded plls (f out 100 mhz) ? ? tbd (1) ps (p-p) period jitter for dedicated clock output in cascaded plls (f out < 100 mhz) ? ? tbd (1) mui (p-p) table 24. pll specifications for cyclone v devices (1) ? preliminary (part 2 of 3) symbol parameter min typ max unit
page 26 switching characteristics cyclone v device datasheet june 2013 altera corporation dsp block specifications table 25 lists the cyclone v dsp block performance specifications. t drift frequency drift after pfdena is disabled for a duration of 100 s ? ? 10 % dk bit bit number of delta sigma modulator (dsm) ? 24 ? bits k value numerator of fraction tbd (1) 8388608 tbd (1) ? f res resolution of vco frequency (f inpfd =100 mhz) ? 5.96 ? hz notes to table 24 : (1) pending silicon characterization. (2) this specification is limited in the quartus ii software by the i/o maximum frequency. the maximum i/o frequency is different for each i/o standard . (3) the vco frequency reported by the quartus ii software takes into consideration the vco post-scale counter k value. therefore, if the counter k has a value of 2, the frequency reported can be lower than the f vco specification. (4) this specification is limited by the lower of the two: i/o f max or f out of the pll. (5) a high input jitter directly affects the pll output jitter. to have low pll output clock jitter, you must provide a clean clock source with jitter < 12 0 ps. (6) f ref is f in / n , specification applies when n =1. (7) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999999974404% confidence level). the output jitter specification applies to the intrinsic jitter of the pll, when an input jitter of 30 ps is applied. the external memory interface clock output jitter specifications use a differ ent measurement method and are available in table 30 on page 1?30 . (8) the cascaded pll specification is only applicable with the following condition: a. upstream pll: 0.59 mhz upstream pll bw < 1 mhz b. downstream pll: downstream pll b w>2mhz (9) high bandwidth pll settings are not supported in external feedback mode. (10) external memory interface clock output jitter specifications use a different measurement method, which is available in table 30 on page 1?30 . table 24. pll specifications for cyclone v devices (1) ? preliminary (part 3 of 3) symbol parameter min typ max unit table 25. dsp block performance specifications for cyclone v devices? preliminary mode performance unit ?c6 ?c7, ?i7 ?c8, ?a7 modes using one dsp block independen t9x9 multiplication 340 300 260 mhz independent 18 x 19 multiplication 287 250 200 mhz independent 18 x 18 multiplication 287 250 200 mhz independent 27 x 27 multiplication 250 200 160 mhz independent 18 x 25 multiplication 310 250 200 mhz independent 20 x 24 multiplication 310 250 200 mhz two 18 x 19 multiplier adder mode 310 250 200 mhz 18 x 18 multiplier added summed with 36-bit input 310 250 200 mhz modes using two dsp blocks complex 18 x 19 multiplication 310 250 200 mhz
switching characteristics page 27 june 2013 altera corporation cyclone v device datasheet memory block specifications table 26 lists the cyclone v memory block specifications. to achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip pll and set to 50% output duty cycle. use the quartus ii software to report timing for the memory block clocking schemes. when you use the error detection cyclical redundancy check (crc) feature, there is no degradation in f max . periphery performance this section describes periphery performance and the high-speed i/o and external memory interface. 1 actual achievable frequency depends on design- and system-specific factors. you must perform hspice/ibis simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. table 26. memory block performance specifications for cyclone v devices? preliminary memory mode resources used performance unit aluts memory ?c6 ?c7, ?i7 ?c8, ?a7 mlab single port, all supported widths 0 1 420 350 300 mhz simple dual-port, all supported widths 0 1 420 350 300 mhz simple dual-port with read and write at the same address 0 1 340 290 240 mhz rom, all supported width 0 1 420 350 300 mhz m10k block single-port, all supported widths 0 1 315 275 240 mhz simple dual-port, all supported widths 0 1 315 275 240 mhz simple dual-port with the read-during-write option set to old data , all supported widths 0 1 275 240 180 mhz true dual port, all supported widths 0 1 315 275 240 mhz rom, all supported widths 0 1 315 275 240 mhz min pulse width (clock high time) ? ? 1,450 1,550 1,650 ps min pulse width (clock low time) ? ? 1,000 1,200 1,350 ps
page 28 switching characteristics cyclone v device datasheet june 2013 altera corporation high-speed i/o specifications table 27 lists high-speed i/o timing for cyclone v devices. table 27. high-speed i/o specifications for cyclone v devices (1), (2), (3) ? preliminary (part 1 of 2) symbol conditions ?c6 ?c7, ?i7 ?c8, ?a7 unit min typ max min typ max min typ max f hsclk_in (input clock frequency) true differential i/o standards clock boost factor w = 1 to 40 (4) 5 ? 437.5 5 ? 420 5 ? 320 mhz f hsclk_in (input clock frequency) single ended i/o standards clock boost factor w = 1 to 40 (4) 5 ? 320 5 ? 320 5 ? 275 mhz f hsclk_out (output clock frequency) ? 5 ? 420 5 ? 370 5 ? 320 mhz transmitter true differential i/o standards - f hsdr (data rate) serdes factor j=4to10 (5) (6) ? 840 (6) ? 740 (6) ? 640 mbps serdes factor j = 1 to 2, uses ddr registers (6) ? (9) (6) ? (9) (6) ? (9) mbps emulated differential i/o standards with three external output resistor networks - f hsdr (data rate) (7) serdes factor j = 4 to 10 (6) ? 640 (6) ? 640 (6) ? 550 mbps emulated differential i/o standards with one external output resistor network - f hsdr (data rate) (7) serdes factor j = 4 to 10 (6) ? 170 (6) ? 170 (6) ? 170 mbps t x jitter - true differential i/o standards total jitter for data rate, 600 mbps - 840 mbps ? ? 350 (8) ? ? 380 (8) ? ? 500 (8) ps total jitter for data rate, < 600 mbps ? ? 0.1 ? ? tbd ? ? tbd ui t x jitter - emulated differential i/o standards with three external output resistor networks total jitter for data rate < 640 mbps ? ? 500 ? ? 500 ? ? 500 ps t x jitter - emulated differential i/o standards with one external output resistor network total jitter for data rate < 640 mbps ? ? 0.15 ? ? 0.15 ? ? 0.15 ui
switching characteristics page 29 june 2013 altera corporation cyclone v device datasheet t duty tx output clock duty cycle for both true and emulated differential i/o standards 45 50 55 45 50 55 45 50 55 % t rise & t fall true differential i/o standards ? ? 200 ? ? 200 ? ? 200 ps emulated differential i/o standards with three external output resistor networks ? ? 250 ? ? 250 ? ? 300 ps emulated differential i/o standards with one external output resistor network ? ? 300 ? ? 300 ? ? 300 ps tccs true differential i/o standards ? ? 200 ? ? 250 ? ? 250 ps emulated differential i/o standards with three external output resistor networks ? ? 300 ? ? 300 ? ? 300 ps emulated differential i/o standards with one external output resistor network ? ? 300 ? ? 300 ? ? 300 ps receiver f hsdr (data rate) serdes factor j=4to10 (5) (6) ? 875 (7) (6) ? 840 (7) (6) ? 640 (7) mbps serdes factor j = 1 to 2, uses ddr registers (6) ? (9) (6) ? (9) (6) ? (9) mbps sampling window ? ? ? 350 ? ? 350 ? ? 350 ps notes to table 27 : (1) whenj=1or2, bypass the serializer/deserializer (serdes) block. (2) for lvds applications, you must use the plls in integer pll mode. (3) this is achieved by using the lvds clock network. (4) clock boost factor (w) is the ratio between the input data rate and the input clock rate. (5) the f max specification is based on the fast clock used for serial data. the interface f max is also dependent on the parallel clock domain which is design dependent and requires timing analysis. (6) the minimum specification depends on the clock source (for example, the pll and clock pin) and the clock routing resource (global, regional, or local) that you use. the i/o differential buffer and input register do not have a minimum toggle rate. (7) you must calculate the leftover timing margin in the receiver by performing link timing closure analysis. you must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin. (8) the specifications are retrieved without partial reconfiguration support. (9) the maximum ideal data rate is the serdes factor (j) x pll max output frequency (f out ), provided you can close the design timing and the signal integrity simulation is clean.you can estimate the achievable maximum data rate by performing link timing closure analysis. you must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. table 27. high-speed i/o specifications for cyclone v devices (1), (2), (3) ? preliminary (part 2 of 2) symbol conditions ?c6 ?c7, ?i7 ?c8, ?a7 unit min typ max min typ max min typ max
page 30 switching characteristics cyclone v device datasheet june 2013 altera corporation dll range, dqs logic block and memory output clock jitter specifications table 28 lists the dll operating frequency range specifications for cyclone v devices. table 29 lists the dqs phase shift error for cyclone v devices. this error specification is the absolute maximum and minimum error. table 30 lists the memory output clock jitter specifications for cyclone v devices. the memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the jedec ddr2/ddr3 sdram standard. the memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (ber) 10 ?12 , equivalent to 14 sigma. altera recommends using the uniphy intellectual property (ip) with phyclk connections for better jitter performance. table 28. dll operating frequency range specifications for cyclone v devices parameter ?c6 ?c7, ?i7 ?c8 unit dll operating frequency range 167 ? 400 167 ? 400 167 ? 333 mhz table 29. dqs phase shift error specification for dll-delayed clock (t dqs_pserr ) for cyclone v devices (1) ? preliminary number of dqs delay buffer ?c6 ?c7, ?i7 ?c8 unit 2408080ps note to table 29 : (1) the numbers are preliminary pending silicon characterization. table 30. memory output clock jitter specification for cyclone v devices? preliminary parameter clock network symbol ?c6 ?c7, ?i7 ?c8 unit min max min max min max clock period jitter phyclk t jit(per) ?90 90 ?90 90 ?90 90 ps cycle-to-cycle period jitter phyclk t jit(cc) 180 180 180 ps
switching characteristics page 31 june 2013 altera corporation cyclone v device datasheet oct calibration block specifications table 31 lists the oct calibration block specifications for cyclone v devices. figure 3 shows the timing diagram for the oe and dyn_term_ctrl signals. duty cycle distortion (dcd) specifications table 32 lists the worst-case dcd for cyclone v devices. the output dcd cycle only applies to the i/o buffer. it does not cover the system dcd. table 31. oct calibration block specifications for cyclone v devices? preliminary symbol description min typ max unit octusrclk clock required by oct calibration blocks ? ? 20 mhz t octcal number of octusrclk clock cycles required for r s oct /r t oct calibration ? 1000 ? cycles t octshift number of octusrclk clock cycles required for oct code to shift out ? 32 ? cycles t rs_rt time required between the dyn_term_ctrl and oe signal transitions in a bidirectional i/o buffer to dynamically switch between r s oct and r t oct ? 2.5 ? ns figure 3. timing diagram for the oe and dyn_term_ctrl signals table 32. worst-case dcd on i/o pins for cyclone v devices? preliminary symbol ?c6 ?c7, ?i7 ?c8, ?a7 unit min max min max min max output duty cycle 45 55 45 55 45 55 % tx rx rx oe dyn_term_ctrl t rs_rt t rs_rt tristate tristate
page 32 switching characteristics cyclone v device datasheet june 2013 altera corporation hps specifications this section provides hps specifications and timing for cyclone v devices. for hps reset, the minimum reset pulse widths for the hps cold and warm reset signals (hps_nrst and hps_npor) are six clock cycles of hps_clk1. the data in table 33 through table 45 is preliminary and pending silicon characterization. hps clock performance table 33 lists the hps clock performance for cyclone v devices. qspi timing characteristics table 34 lists the queued serial peripheral interface (qspi) timing characteristics for cyclone v devices. figure 4 shows the timing diagram for qspi timing characteristics. table 33. hps clock performance for cyclone v devices? preliminary symbol/description ?c6 ?c7, ?i7 ?c8, ?a7 unit mpu_base_clk 800 800 600 mhz main_base_clk 400 400 300 mhz table 34. qspi timing requirements for cyclone v devices? preliminary symbol description min typ max unit f clk clk clock frequency ? ? 108 mhz t dutycycle qspi_clk duty cycle tbd ? tbd % t dssfrst output delay qspi_ss valid before first clock edge 8 ? tbd ns t dsslst output delay qspi_ss valid after last clock edge 8 ? tbd ns t dio io data output delay ?1 ? 1 ns t dinmax maximum data input delay from falling edge of qspi_clk to data arrival at soc ? ? 20 ns figure 4. qspi timing diagram qspi_ss qspi_clk qspi_data t dinmax t dsslst t dio t dssfrst data out data in
switching characteristics page 33 june 2013 altera corporation cyclone v device datasheet spi timing characteristics table 35 lists the serial peripheral interface (spi) master timing characteristics for cyclone v devices. the setup and hold times can be used for texas instruments ssp mode and national semiconductor microwire mode. figure 5 shows the timing diagram for spi master timing characteristics. table 36 lists the spi slave timing characteristics for cyclone v devices. the setup and hold times can be used for texas instruments ssp mode and national semiconductor microwire mode. table 35. spi master timing requirements for cyclone v devices? preliminary symbol description min typ max unit t clk clk clock period tbd 20 tbd ns t dutycycle spi_clk duty cycle tbd ? tbd % t dssfrst output delay spi_ss valid before first clock edge 8 ? tbd ns t dsslst output delay spi_ss valid after last clock edge 8 ? tbd ns t dio master-out slave-in (mosi) output delay ?1 ? 1 ns t dinmax maximum data input delay from falling edge of spi_clk to data arrival at soc ? ? 500 ns figure 5. spi master timing diagram spi_ss spi_clk (scpol = 0) spi_mosi (scph = 1) spi_miso (scph = 1) t dssfrst spi_clk (scpol = 1) spi_mosi (scph = 0) spi_miso (scph = 0) t dio t dio t dinmax t dinmax t dsslst table 36. spi slave timing requirements for cyclone v devices? preliminary (part 1 of 2) symbol description min typ max unit t clk clk clock period tbd 20 tbd ns t s mosi setup time 5 ? tbd ns t h mosi hold time 5 ? tbd ns t suss setup time spi_ss valid before first clock edge 8 ? tbd ns
page 34 switching characteristics cyclone v device datasheet june 2013 altera corporation figure 6 shows the timing diagram for spi slave timing characteristics. sd/mmc timing characteristics table 37 lists the secure digital (sd)/multimediacard (mmc) timing characteristics for cyclone v devices. t hss hold time spi_ss valid after last clock edge 8 ? tbd ns t d master-in slave-out (miso) output delay tbd ? 6 ns table 36. spi slave timing requirements for cyclone v devices? preliminary (part 2 of 2) symbol description min typ max unit figure 6. spi slave timing diagram spi_ss spi_clk (scpol = 0) spi_mosi (scph = 1) spi_miso (scph = 1) spi_clk (scpol = 1) spi_mosi (scph = 0) spi_miso (scph = 0) t suss t d t d t s t h t s t h t hss table 37. sd/mmc timing requirements for cyclone v devices? preliminary symbol description min max unit t clk sdmmc_clk_out clock period 20 tbd ns t dutycycle sdmmc_clk_out duty cycle tbd tbd % t d sdmmc_cmd/sdmmc_d output delay tbd 6 ns t dinmax maximum input delay from rising edge of sdmmc_clk to data arrival at soc ?25ns
switching characteristics page 35 june 2013 altera corporation cyclone v device datasheet figure 7 shows the timing diagram for sd/mmc timing characteristics. usb timing characteristics table 38 lists the usb timing characteristics for cyclone v devices. figure 8 shows the timing diagram for usb timing characteristics. ethernet media access controller (emac) timing characteristics table 39 lists the reduced gigabit media independent interface (rgmii) tx timing characteristics for cyclone v devices. figure 7. sd/mmc timing diagram command/data in sdmmc_clk_out sdmmc_cmd & sdmmc_d (out) sdmmc_cmd & sdmmc_d (in) command/data out t dinmax t d table 38. usb timing requirements for cyclone v devices? preliminary symbol description min typ max unit t clk usb clk clock period tbd 16.67 tbd ns t d clk to usb_stp/usb_data[7:0] output delay tbd ? 8 ns t su setup time for usb_dir/usb_nxt/usb_data[7:0] 2 ? tbd ns t h hold time for usb_dir/usb_nxt/usb_data[7:0] 1.5 ? tbd ns figure 8. usb timing diagram usb_clk usb_stp usb_data[7:0] usb_dir & usb_nxt to phy from phy t su t h t d table 39. rgmii tx timing requirements for cyclone v devices? preliminary symbol description min typ max unit t clk (1000base-t) tx_clk clock period tbd 8 tbd ns t clk (100base-t) tx_clk clock period tbd 40 tbd ns t clk (10base-t) tx_clk clock period tbd 400 tbd ns t dutycycle tx_clk duty cycle tbd ? tbd % t d tx_clk to txd/tx_ctl output data delay ?0.5 ? 0.5 ns
page 36 switching characteristics cyclone v device datasheet june 2013 altera corporation figure 9 shows the timing diagram for rgmii tx timing characteristics. table 40 lists the rgmii rx timing characteristics for cyclone v devices. figure 10 shows the timing diagram for rgmii rx timing characteristics. table 41 lists the management data input/output (mdio) timing characteristics for cyclone v devices. figure 9. rgmii tx timing diagram tx_clk tx_d[3:0] tx_ctl t d table 40. rgmii rx timing requirements for cyclone v devices? preliminary symbol description min typ max unit t clk (1000base-t) rx_clk clock period tbd 8 tbd ns t clk (100base-t) rx_clk clock period tbd 40 tbd ns t clk (10base-t) rx_clk clock period tbd 400 tbd ns t su rx_d/rx_ctl setup time 1 ? tbd ns t h rx_d/rx_ctl hold time 1 ? tbd ns figure 10. rgmii rx timing diagram rx_clk rx_d[3:0] rx_ctl t su t h table 41. mdio timing requirements for cyclone v devices? preliminary symbol description min typ max unit t clk mdc clock period tbd 400 tbd ns t d mdc to mdio output data delay 10 ? tbd ns t s setup time for mdio data 10 ? tbd ns t h hold time for mdio data 10 ? tbd ns
switching characteristics page 37 june 2013 altera corporation cyclone v device datasheet figure 11 shows the timing diagram for mdio timing characteristics. i 2 c timing characteristics table 42 lists the i 2 c timing characteristics for cyclone v devices. figure 12 shows the timing diagram for i 2 c timing characteristics. nand timing characteristics table 43 lists the nand timing characteristics for cyclone v devices. figure 11. mdio timing diagram mdc mdio_out mdio_in t su t h t d table 42. i 2 c timing requirements for cyclone v devices? preliminary symbol description standard mode fast mode unit min max min max t clk serial clock (scl) clock period tbd 10 tbd 2.5 s t clkhigh scl high time 4 tbd 0.6 tbd s t clklow scl low time 4.7 tbd 1.3 tbd s t s setup time for serial data line (sda) data to scl 250 tbd 100 tbd ns t h hold time for scl to sda data tbd 3.45 tbd 0.9 s t d scl to sda output data delay 8 tbd 8 tbd ns figure 12. i 2 c timing diagram data in t d data out i2c_scl i2c_sda t s t h table 43. nand onfi 1.0 timing requirements for cyclone v devices? preliminary (part 1 of 2) symbol description min max unit t wp write enable pulse width 10 tbd ns t wh write enable hold time 7 tbd ns t rp read enable pulse width 10 tbd ns t reh read enable holdtime 7 tbd ns t clesu command latch enable to write enable setup time 10 tbd ns t cleh command latch enable to write enable hold time 5 tbd ns
page 38 switching characteristics cyclone v device datasheet june 2013 altera corporation figure 13 shows the timing diagram for nand command latch timing characteristics. t cesu chip enable to write enable setup time 15 tbd ns t ceh chip enable to write enable hold time 5 tbd ns t alesu address latch enable to write enable setup time 10 tbd ns t aleh address latch enable to write enable hold time 5 tbd ns t dsu data to write enable setup time 10 tbd ns t dh data to write enable hold time 5 tbd ns t drb write enable high to ready/busy low tbd 100 ns t cea chip enable to data access time tbd 25 ns t rea read enable to data access time tbd 16 ns t rhz read enable to data high impedance tbd 100 ns t rb ready to read enable low 20 tbd ns table 43. nand onfi 1.0 timing requirements for cyclone v devices? preliminary (part 2 of 2) symbol description min max unit figure 13. nand command latch timing diagram command nand_cle nand_ce nand_we nand_ale nand_dq[7:0] nand_rb t clesu t cesu t ceh t cleh t wp t alesu t aleh t dsu t dh t drb
switching characteristics page 39 june 2013 altera corporation cyclone v device datasheet figure 14 shows the timing diagram for nand address latch timing characteristics. figure 15 shows the timing diagram for nand data write timing characteristics. figure 14. nand address latch timing diagram address nand_cle nand_we nand_ale nand_dq[7:0] t clesu t cesu t wh t wp t alesu t aleh t dsu t dh nand_ce figure 15. nand data write timing diagram nand_cle nand_we nand_ale nand_dq[7:0] t ceh t cleh t wp t alesu t dsu t dh nand_ce din
page 40 switching characteristics cyclone v device datasheet june 2013 altera corporation figure 16 shows the timing diagram for nand data read timing characteristics. arm trace timing characteristics table 44 lists the arm trace timing characteristics for cyclone v devices. uart interface the maximum uart baud rate is 6.25 megasymbols per second. gpio interface table 45 lists the general-purpose i/o (gpio) pulse width for cyclone v devices. can interface the maximum controller area network (can) data rate is 1 mbps. figure 16. nand data read timing diagram t rb nand_re nand_rb nand_dq[7:0] nand_ce dout t cea t rp t reh t rea t rhz table 44. arm trace timing requirements for cyclone v devices? preliminary description min typ max unit clk clock period tbd 8 tbd ns clk maximum duty cycle tbd ? tbd % clk to d0 ?d7 output data delay ?1 ? 1 ns table 45. gpio pulse width for cyclone v devices? preliminary description min max unit minimum detectable pulse width 40 tbd ns
configuration specification page 41 june 2013 altera corporation cyclone v device datasheet configuration specification this section provides configuration specifications and timing for cyclone v devices. por specifications table 46 lists the specifications for fast and standard por delay for cyclone v devices. jtag configuration timing table 47 lists the jtag timing parameters and values for cyclone v devices. table 46. fast and standard por delay specification for cyclone v devices (1) por delay minimum maximum unit fast (2) 412ms standard 100 300 ms notes to table 46 : (1) select the por delay based on the msel setting as described in the ?configuration schemes for cyclone v devices? table in the configuration, design security, and remote system upgrades in cyclone v devices chapter. (2) the maximum pulse width of the fast por delay is 12 ms, providing enough time for the pcie hard ip to initialize after the por trip. table 47. jtag timing parameters and values for cyclone v devices? preliminary symbol description min max unit t jcp tck clock period 30 ? ns t jcp tck clock period 167 (1) ?ns t jch tck clock high time 14 ? ns t jcl tck clock low time 14 ? ns t jpsu (tdi) tdi jtag port setup time 1 ? ns t jpsu (tms) tms jtag port setup time 3 ? ns t jph jtag port hold time 5 ? ns t jpco jtag port clock to output ? 11 (2) ns t jpzx jtag port high impedance to valid output ? 14 (2) ns t jpxz jtag port valid output to high impedance ? 14 (2) ns notes to table 47 : (1) the minimum tck clock period is 167 ns if v ccbat is within the range 1.2 v ? 1.5 v when you perform the volatile key programming. (2) a 1 ns adder is required for each v ccio voltage step down from 3.0 v. for example, t jpco =12nsifv ccio of the tdo i/o bank = 2.5 v, or 13 ns if it equals 1.8 v.
page 42 configuration specification cyclone v device datasheet june 2013 altera corporation fpp configuration timing this section describes the fast passive parallel (fpp) configuration timing parameters for cyclone v devices. dclk-to-data[] ratio (r) for fpp configuration fpp configuration requires a different dclk -to- data[] ratio when you turn on encryption or the compression feature. depending on the dclk-to-data[] ratio, the host must send a dclk frequency that is r times the data[] rate in byte per second (bps) or word per second (wps). for example, in fpp x16 where the r is 2, the dclk frequency must be 2 times the data[] rate in wps. cyclone v devices use additional clock cycles to decrypt and decompress the configuration data. table 48 lists the dclk -to- data[] ratio for each combination. 1 if the dclk -to- data[] ratio is greater than 1, at the end of configuration, you can only stop the dclk ( dclk -to- data[] ratio ? 1) clock cycles after the last data is latched into the cyclone v device. table 48. dclk-to-data[] ratio for cyclone v devices? preliminary configuration scheme encryption compression dclk-to-data[] ratio (r) fpp (8-bit wide) off off 1 on off 1 off on 2 on on 2 fpp (16-bit wide) off off 1 on off 2 off on 4 on on 4
configuration specification page 43 june 2013 altera corporation cyclone v device datasheet fpp configuration timing when dclk to data[] = 1 figure 17 shows the timing waveform for an fpp configuration when using a max ? ii device as an external host. this waveform shows timing when the dclk -to- data[] ratio is 1. 1 when you enable decompression or the design security feature, the dclk -to- data[] ratio varies for fpp x8 and fpp x16. for the respective dclk -to- data[] ratio, refer to table 48 on page 1?42 . figure 17. dclk-to-data[] fpp configuration timing waveform for cyclone v devices when the ratio is 1 (1) notes to figure 17 : (1) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus , and conf_done are at logic-high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) after power up, the cyclone v device holds nstatus low for the time of the por delay. (3) after power up, before and during configuration, conf_done is low. (4) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (5) for fpp x16, use data[15..0] . for fpp x8, use data[7..0] . data[15..0] are available as a user i/o pin after configuration. the state of this pin depends on the dual-purpose pin settings. (6) to ensure a successful configuration, send the entire configuration data to the cyclone v device. conf_done is released high when the cyclone v device receives all the configuration data successfully. after conf_done goes high, send two additional falling edges on dclk to begin initialization and enter user mode. (7) after the option bit to enable the init_done pin is configured into the device, init_done goes low. nconfig nstatus (2) conf_done (3) dclk data[15..0] user i/o init_done word 0 word 1 word 2 word 3 t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mode (5) (7) (4) user mode word n-2 word n-1 (6)
page 44 configuration specification cyclone v device datasheet june 2013 altera corporation table 49 lists the timing parameters for cyclone v devices for an fpp configuration when the dclk -to- data[] ratio is 1. table 49. dclk-to-data[] fpp timing parameters for cyclone v devices when the ratio is 1? preliminary symbol parameter minimum maximum unit t cf2cd nconfig low to conf_done low ? 600 ns t cf2st0 nconfig low to nstatus low ? 600 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 268 1506 (1) s t cf2st1 nconfig high to nstatus high ? 1506 (2) s t cf2ck nconfig high to first rising edge on dclk 1506 ? s t st2ck nstatus high to first rising edge of dclk 2?s t dsu data[] setup time before rising edge on dclk 5.5 ? ns t dh data[] hold time after rising edge on dclk 0?ns t ch dclk high time 0.45 x 1/f max ?s t cl dclk low time 0.45 x 1/f max ?s t clk dclk period 1/f max ?s f max dclk frequency (fpp x8 and x16) ? 125 mhz t cd2um conf_done high to user mode (3) 175 437 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu +(t init x clkusr period) ?? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 49 : (1) you can obtain this value if you do not delay configuration by extending the nconfig or nstatus low pulse width. (2) you can obtain this value if you do not delay configuration by externally holding nstatus low. (3) the minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
configuration specification page 45 june 2013 altera corporation cyclone v device datasheet fpp configuration timing when dclk to data[] > 1 figure 18 shows the timing waveform for an fpp configuration when using a max ii device or microprocessor as an external host. this waveform shows timing when the dclk -to- data[] ratio is more than 1. figure 18. fpp configuration timing waveform for cyclone v devices when the dclk-to-data[] ratio is > 1 (1) notes to figure 18 : (1) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) after power up, the cyclone v device holds nstatus low for the time as specified by the por delay. (3) after power up, before and during configuration, conf_done is low. (4) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (5) ?r? denotes the dclk -to- data[] ratio. for the dclk -to- data[] ratio based on the decompression and the design security feature enable settings, refer to table 48 on page 1?42 . (6) if needed, pause dclk by holding it low. when dclk restarts, the external host must provide data on the data[15..0] pins prior to sending the first dclk rising edge. (7) to ensure a successful configuration, send the entire configuration data to the cyclone v device. conf_done is released high after the cyclone v device receives all the configuration data successfully. after conf_done goes high, send two additional falling edges on dclk to begin initialization and enter user mode. (8) after the option bit to enable the init_done pin is configured into the device, init_done goes low. nconfig nstatus (2) conf_done (3) dclk (5) data[15..0] (7) user i/o init_done t cd2um t cf2st1 t cf2cd t cfg t cf2ck t t cf2st0 t st2ck high-z user mod 12 r 12 r 12 word 0 word 1 word 3 1 t dsu t dh status t dh t ch t cl t clk word ( n -1) (6) (7) (8) (4) user mod r
page 46 configuration specification cyclone v device datasheet june 2013 altera corporation table 50 lists the timing parameters for cyclone v devices when the dclk -to- data[] ratio is more than 1. table 50. dclk-to-data[] fpp timing parameters for cyclone v devices when the ratio is > 1 (1) ? preliminary symbol parameter minimum maximum unit t cf2cd nconfig low to conf_done low ? 600 ns t cf2st0 nconfig low to nstatus low ? 600 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 268 1506 (2) s t cf2st1 nconfig high to nstatus high ? 1506 (3) s t cf2ck nconfig high to first rising edge on dclk 1506 ? s t st2ck nstatus high to first rising edge of dclk 2?s t dsu data[] setup time before rising edge on dclk 5.5 ? ns t dh data[] hold time after rising edge on dclk n ? 1/f dclk (4) ?s t ch dclk high time 0.45 x 1/f max ?s t cl dclk low time 0.45 x 1/f max ?s t clk dclk period 1/f max ?s f max dclk frequency (fpp x8 and x16) ? 125 mhz t r input rise time ? 40 ns t f input fall time ? 40 ns t cd2um conf_done high to user mode (5) 175 437 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu +(t init x clkusr period) ?? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 50 : (1) use these timing parameters when you use decompression and the design security features. (2) this value can be obtained if you do not delay configuration by extending the nconfig or nstatus low pulse width. (3) this value can be obtained if you do not delay configuration by externally holding nstatus low. (4) n is the dclk -to- data[] ratio and f dclk is the dclk frequency of the system. (5) the minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
configuration specification page 47 june 2013 altera corporation cyclone v device datasheet as configuration timing figure 19 shows the timing waveform for the active serial (as) x1 mode and as x4 mode configuration timing. table 51 lists the timing parameters for as x1 and as x4 configurations in cyclone v devices. the minimum and maximum numbers apply to both the internal oscillator and clkusr when either one is used as the clock source for device configuration. the t cf2cd ,t cf2st0 ,t cfg ,t status , and t cf2st1 timing parameters are identical to the timing parameters for passive serial (ps) mode listed in table 53 on page 1?49 .you can obtain the t cf2st1 value if you do not delay configuration by externally holding nstatus low. figure 19. as configuration timing waveform for cyclone v devices notes to figure 19 : (1) if you are using as x4 mode, this signal represents the as_data[3..0] and epcq sends in 4-bits of data for each dclk cycle. (2) the initialization clock can be from the internal oscillator or the clkusr pin. (3) after the option bit to enable the init_done pin is configured into the device, init_done goes low. read address bit 1 bit 0 bit ( n ? 2) bit ( n ? 1) t cd2um nstatus nconfig conf_done ncso dclk as_data0/asdo as_data1 (1) init_done (3) user i/o user mode t cf2st1 t dh t su t co (2) table 51. as timing parameters for as x1 and x4 configurations in cyclone v devices? preliminary symbol parameter minimum maximum unit t co dclk falling edge to the as_data0 / asdo output ? 4 s t su data setup time before the falling edge on dclk 1.5 ? ns t dh data hold time after the falling edge on dclk 0?ns t cd2um conf_done high to user mode 175 437 s t cd2cu conf_done high to clkusr enabled 4 x maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu +(t init x clkusr period) ?? t init number of clock cycles required for device initialization 17,408 ? cycles
page 48 configuration specification cyclone v device datasheet june 2013 altera corporation table 52 lists the internal clock frequency specification for the as configuration scheme. the dclk frequency specification applies when you use the internal oscillator as the configuration clock source. the as multi-device configuration scheme does not support dclk frequency of 100 mhz. ps configuration timing figure 20 shows the timing waveform for a ps configuration when using a max ii device or microprocessor as an external host. table 52. dclk frequency specification in the as configuration scheme for cyclone v devices? preliminary parameter minimum typical maximum unit dclk frequency in as configuration scheme 5.3 7.9 12.5 mhz 10.6 15.7 25.0 mhz 21.3 31.4 50.0 mhz 42.6 62.9 100.0 mhz remote update only in as mode ? ? 12.5 mhz figure 20. ps configuration timing waveform for cyclone v devices (1) notes to figure 20 : (1) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) after power up, the cyclone v device holds nstatus low for the time of the por delay. (3) after power up, before and during configuration, conf_done is low. (4) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (5) to ensure a successful configuration, send the entire configuration data to the cyclone v device. conf_done is released high after the cyclone v device receives all the configuration data successfully. after conf_done goes high, send two additional falling edges on dclk to begin initialization and enter user mode. (6) after the option bit to enable the init_done pin is configured into the device, init_done goes low. nconfig nstatus (2) conf_done (3) dclk data0 user i/o init_done (6) bit 0 bit 1 bit 2 bit 3 bit ( n-1) t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mo d (5) (4)
configuration specification page 49 june 2013 altera corporation cyclone v device datasheet table 53 lists the ps timing parameter for cyclone v devices. table 53. ps timing parameters for cyclone v devices? preliminary symbol parameter minimum maximum unit t cf2cd nconfig low to conf_done low ? 600 ns t cf2st0 nconfig low to nstatus low ? 600 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 268 1506 (1) s t cf2st1 nconfig high to nstatus high ? 1506 (2) s t cf2ck nconfig high to first rising edge on dclk 1506 ? s t st2ck nstatus high to first rising edge of dclk 2?s t dsu data[] setup time before rising edge on dclk 5.5 ? ns t dh data[] hold time after rising edge on dclk 0?ns t ch dclk high time 0.45 x 1/f max ?s t cl dclk low time 0.45 x 1/f max ?s t clk dclk period 1/f max ?s f max dclk frequency ? 125 mhz t cd2um conf_done high to user mode (3) 175 437 s t cd2cu conf_done high to clkusr enabled 4 x maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu +(t init x clkusr period) ? ? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 53 : (1) you can obtain this value if you do not delay configuration by extending the nconfig or nstatus low pulse width. (2) you can obtain this value if you do not delay configuration by externally holding nstatus low. (3) the minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
page 50 configuration specification cyclone v device datasheet june 2013 altera corporation initialization table 54 lists the initialization clock source option, the applicable configuration schemes, and the maximum frequency for cyclone v devices. configuration files use table 55 to estimate the file size before design compilation. different configuration file formats, such as a hexadecimal file ( .hex ) or tabular text file ( .ttf ) format, have different file sizes. for the different types of configuration file and file sizes, refer to the quartus ii software. however, for a specific version of the quartus ii software, any design targeted for the same device has the same uncompressed configuration file size. table 55 lists the uncompressed raw binary file ( .rbf ) sizes for cyclone v devices. table 54. initialization clock source option and the maximum frequency for cyclone v devices initialization clock source configuration schemes maximum frequency (mhz) minimum number of clock cycles internal oscillator as, ps, and fpp 12.5 t init clkusr (1) ps and fpp 125 as 100 note to table 54 : (1) to enable clkusr as the initialization clock source, turn on the enable user-supplied start-up clock ( clkusr ) option in the quartus ii software from the general panel of the device and pin options dialog box. table 55. uncompressed .rbf sizes for cyclone v devices ?preliminary (part 1 of 2) variant member code configuration .rbf size (bits) iocsr .rbf size (bits) cyclone v e (1) a2 21,061,120 275,608 a4 21,061,120 275,608 a5 33,958,336 322,072 a7 56,167,328 435,288 a9 102,871,552 400,408 cyclone v gx c3 14,512,096 320,280 c4 33,958,336 322,072 c5 33,958,336 322,072 c7 56,167,328 435,288 c9 102,871,552 400,408 cyclone v gt d5 33,958,336 322,072 d7 56,167,328 435,288 d9 102,871,552 400,408 cyclone v se (1) a2 (2) 33,958,336 322,072 a4 (2) 33,958,336 322,072 a5 56,057,408 324,888 a6 56,057,408 324,888
configuration specification page 51 june 2013 altera corporation cyclone v device datasheet table 56 lists the minimum configuration time estimation for cyclone v devices. the estimated values are based on the configuration .rbf sizes in table 55 . cyclone v sx c2 (2) 33,958,336 322,072 c4 (2) 33,958,336 322,072 c5 56,057,408 324,888 c6 56,057,408 324,888 cyclone v st d5 56,057,408 324,888 d6 56,057,408 324,888 notes to table 55 : (1) no pcie hard ip, configuration via protocol (cvp) is not supported in this family. (2) this device will be supported in a future release of the quartus ii software. table 55. uncompressed .rbf sizes for cyclone v devices ?preliminary (part 2 of 2) variant member code configuration .rbf size (bits) iocsr .rbf size (bits) table 56. minimum configuration time estimation for cyclone v devices ?preliminary (part 1 of 2) variant member code active serial (1) fast passive parallel (2) width dclk (mhz) minimum configuration time (ms) width dclk (mhz) minimum configuration time (ms) cyclone v e a2 4 100 53 16 125 11 a4 4 100 53 16 125 11 a5 4 100 85 16 125 17 a7 4 100 140 16 125 28 a9 4 100 257 16 125 51 cyclone v gx c3 4 100 36 16 125 7 c4 4 100 85 16 125 17 c5 4 100 85 16 125 17 c7 4 100 140 16 125 28 c9 4 100 257 16 125 51 cyclone v gt d5 4 100 85 16 125 17 d7 4 100 140 16 125 28 d9 4 100 257 16 125 51 cyclone v se a2 4 100 85 16 125 17 a4 4 100 85 16 125 17 a5 4 100 140 16 125 28 a6 4 100 140 16 125 28 cyclone v sx c2 4 100 85 16 125 17 c4 4 100 85 16 125 17 c5 4 100 140 16 125 28 c6 4 100 140 16 125 28
page 52 configuration specification cyclone v device datasheet june 2013 altera corporation remote system upgrades circuitry timing specification table 57 lists the timing parameter specifications for the remote system upgrade circuitry. user watchdog internal oscillator frequency specification table 58 lists the frequency specifications for the user watchdog internal oscillator. cyclone v st d5 4 100 140 16 125 28 d6 4 100 140 16 125 28 notes to table 55 : (1) dclk frequency of 100 mhz using external clkusr . (2) maximum fpga fpp bandwidth may exceed bandwidth available from some external storage or control logic. table 56. minimum configuration time estimation for cyclone v devices ?preliminary (part 2 of 2) variant member code active serial (1) fast passive parallel (2) width dclk (mhz) minimum configuration time (ms) width dclk (mhz) minimum configuration time (ms) table 57. remote system upgrade circuitry timing specification for cyclone v devices? preliminary parameter minimum maximum unit t max_ru_clk (1) ? 40 mhz t ru_nconfig (2) 250 ? ns t ru_nrstimer (3) 250 ? ns notes to table 57 : (1) this clock is user-supplied to the remote system upgrade circuitry. if you are using the altremote_update megafunction, the clock user-supplied to the altremote_update megafunction must meet this specification. (2) this is equivalent to strobing the reconfiguration input of the altremote_update megafunction high for the minimum timing specification. for more information, refer to the ?remote system upgrade state machine? section in the configuration, design security, and remote system upgrades in cyclone v devices chapter. (3) this is equivalent to strobing the reset timer input of the altremote_update megafunction high for the minimum timing specification. for more information, refer to the ?user watchdog timer? section in the configuration, design security, and remote system upgrades in cyclone v devices chapter. table 58. user watchdog internal oscillator frequency specifications for cyclone v devices? preliminary parameter minimum typical maximum unit user watchdog internal oscillator frequency 5.3 7.9 12.5 mhz
i/o timing page 53 june 2013 altera corporation cyclone v device datasheet i/o timing altera offers two ways to determine i/o timing?the excel-based i/o timing and the quartus ii timing analyzer. excel-based i/o timing provides pin timing performance for each device density and speed grade. the data is typically used prior to designing the fpga to get an estimate of the timing budget as part of the link timing analysis. the quartus ii timing analyzer provides a more accurate and precise i/o timing data based on the specifics of the design after you complete place-and-route. f you can download the excel-based i/o timing spreadsheet from the cyclone v devices documentation webpage. programmable ioe delay table 59 lists the cyclone v ioe programmable delay settings. programmable output buffer delay table 60 lists the delay chain settings that control the rising and falling edge delays of the output buffer. the default delay is 0 ps. you can set the programmable output buffer delay in the quartus ii software by setting the output buffer delay control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the output buffer delay assignment. table 59. ioe programmable delay for cyclone v devices parameter available settings minimum offset fast model slow model unit industrial commercial ?c6 ?c7 ?c8 ?i7 ?a7 d1 31 0 0.508 0.517 0.971 1.187 1.194 1.179 1.160 ns d3 7 0 1.761 1.793 3.291 4.022 3.961 3.999 3.929 ns d4 31 0 0.510 0.519 1.180 1.187 1.195 1.180 1.160 ns d5 31 0 0.508 0.517 0.970 1.186 1.194 1.179 1.179 ns table 60. programmable output buffer delay for cyclone v devices (1) ? preliminary symbol parameter typical unit d outbuf rising and/or falling edge delay 0 (default) ps 50 ps 100 ps 150 ps note to table 60 : (1) pending data extraction from the quartus ii software.
page 54 glossary cyclone v device datasheet june 2013 altera corporation glossary table 61 lists the glossary for this datasheet. table 61. glossary table (part 1 of 4) letter subject definitions a b c ?? d differential i/o standards receiver input waveforms transmitter output waveforms e ?? f f hsclk left/right pll input clock frequency. f hsdr high-speed i/o block?maximum/minimum lvds data transfer rate (f hsdr = 1/tui). g h i ?? single-ended waveform differential waveform positive channel (p) = v ih n egative channel (n) = v il gro u nd v id v id v id p ? n = 0 v v cm single-ended waveform differential waveform positive channel (p) = v oh n egative channel (n) = v ol gro u nd v od v od v od p ? n = 0 v v cm
glossary page 55 june 2013 altera corporation cyclone v device datasheet j j high-speed i/o block?deserialization factor (width of parallel data bus). jtag timing specifications jtag timing specifications: k l m n o ?? p pll specifications diagram of pll specifications (1) note: (1) core clock can only be fed by dedicated clock input pins or pll outputs. preliminary some tables show the designation as ?preliminary?. preliminary characteristics are created using simulation results, process data, and other known parameters. final numbers are based on actual silicon characterization and testing. the numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. there are no preliminary designations on finalized tables. q ?? r r l receiver differential input discrete resistor (external to the cyclone v device). table 61. glossary table (part 2 of 4) letter subject definitions tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms core clock external feedback reconfigurable in user mode key clk n pfd switchover delta sigma modulator vco cp lf clkout pins gclk rclk f inpfd f in f vco f out f out_ext counters c0..c17 4
page 56 glossary cyclone v device datasheet june 2013 altera corporation s sampling window (sw) timing diagram?the period of time during which the data must be valid in order to capture it correctly. the setup and hold times determine the ideal strobe position within the sampling window, as shown: single-ended voltage referenced i/o standard the jedec standard for the sstl and hstl i/o defines both the ac and dc input signal values. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. after the receiver input has crossed the ac value, the receiver changes to the new logic state. the new logic state is then maintained as long as the input stays beyond the dc threshold. this approach is intended to provide predictable receiver timing in the presence of input waveform ringing. single-ended voltage referenced i/o standard t t c high-speed receiver/transmitter input and output clock period. tccs (channel- to-channel-skew) the timing difference between the fastest and slowest output edges, including the t co variation and clock skew, across channels driven by the same pll. the clock is included in the tccs measurement (refer to the timing diagram figure under sw in this table). t duty high-speed i/o block?duty cycle on high-speed transmitter output clock. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and the data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ) t fall signal high-to-low transition time (80-20%) t inccj cycle-to-cycle jitter tolerance on the pll clock input t outpj_io period jitter on the general purpose i/o driven by a pll t outpj_dc period jitter on the dedicated clock output driven by a pll t rise signal low-to-high transition time (20?80%) u ?? table 61. glossary table (part 3 of 4) letter subject definitions bit time 0.5 x tccs rskm sampling w indow (s w ) rskm 0.5 x tccs v ih ( ac ) v ih(dc) v ref v il(dc) v il(ac ) v oh v ol v ccio v ss
document revision history page 57 june 2013 altera corporation cyclone v device datasheet document revision history table 62 lists the revision history for this document. v v cm(dc) dc common mode input voltage. v icm input common mode voltage?the common mode of the differential signal at the receiver. v id input differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. v dif(ac) ac differential input voltage?minimum ac input differential voltage required for switching. v dif(dc) dc differential input voltage? minimum dc input differential voltage required for switching. v ih voltage input high?the minimum positive voltage applied to the input which is accepted by the device as a logic high. v ih(ac) high-level ac input voltage v ih(dc) high-level dc input voltage v il voltage input low?the maximum positive voltage applied to the input which is accepted by the device as a logic low. v il(ac) low-level ac input voltage v il(dc) low-level dc input voltage v ocm output common mode voltage?the common mode of the differential signal at the transmitter. v od output differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. v swing differential input voltage v x input differential cross point voltage v ox output differential cross point voltage w w high-speed i/o block?clock boost factor x y z ?? table 61. glossary table (part 4 of 4) letter subject definitions table 62. document revision history (part 1 of 2) date version changes june 2013 3.4 updated table 20 , table 27 , and table 34 . updated ?uart interface? and ?can interface? sections. removed the following tables: table 45. uart baud rate for cyclone v devices table 47. can pulse width for cyclone v devices may 2013 3.3 added table 33. updated figure 5, figure 6, figure 17, figure 19, and figure 20. updated table 1, table 4, table 5, table 10, table 13, table 19, table 20, table 26, table 32, table 35, table 36, table 43, table 53, table 54, table 57, and table 61.
page 58 document revision history cyclone v device datasheet june 2013 altera corporation march 2013 3.2 added hps reset information in the ?hps specifications? section. added table 57. updated table 1, table 2, table 17, table 20, table 52, and table 56. updated figure 18. january 2013 3.1 updated table 4, table 20, and table 56. november 2012 3.0 updated table 1, table 4, table 5, table 9, table 14, table 16, table 17, table 19, table 20, table 25, table 28, table 52, table 55, table 56, and table 59. removed table: transceiver block jitter specifications for cyclone v gx devices. added hps information: added ?hps specifications? section. added table 33, table 34, table 35, table 36, table 37, table 38, table 39, table 40, table 41, table 42, table 43, table 44, table 45, and table 46. added figure 4, figure 5, figure 6, figure 7, figure 8, figure 9, figure 10, figure 11, figure 12, figure 13, figure 14, figure 15, and figure 16. updated table 3. june 2012 2.0 updated for the quartus ii software v12.0 release: restructured document. removed ?power consumption? section. updated table 1,table 3, table 19, table 20, table 25, table 27, table 28, table 30, table 31, table 34, table 36, table 37, table 38, table 39, table 41, table 43, and table 46. added table 22, table 23, and table 29. added figure 1 and figure 2. added ?initialization? and ?configuration files? sections. february 2012 1.2 added automotive speed grade information. added figure 2?1. updated table 2?3, table 2?8, table 2?9, table 2?19, table 2?20, table 2?21, table 2?22, table 2?23, table 2?24, table 2?25, table 2?26, table 2?27, table 2?28, table 2?30, table 2?35, and table 2?43. minor text edits. november 2011 1.1 added table 2?5. updated table 2?3, table 2?4, table 2?11, table 2?13, table 2?20, and table 2?21. october 2011 1.0 initial release. table 62. document revision history (part 2 of 2) date version changes

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